[Triton-SPIRV] General idea and question on Triton

[chengjunlu]

Hi @ptillet ,

I am bringing up the Triton on Intel GPU.

The integration idea is naively thru:
TritonIR -> LLVM with SPIRV intrinsic -> SPV kernel -> SYCL runtime to run the kernel on Intel GPU platform.

All the required components are available in github.
Intel SYCL runtime:
https://github.com/intel/llvm
Intel Graphic compute platform:
https://github.com/intel/compute-runtime

The PoC shows a promising result with Triton.

But I meet some coupled issue in integration and I think the Triton is coupled with CUDA too much.

My questions are:

1. How to co-work with the Triton project to contribute my integration to Triton?
2. What is the status of the Triton-MLIR? I hope the Triton-MLIR decouple the logic with CUDA on some aspect.

Looking forward your feedback and comments.

Thanks
John

[ptillet]

Hello,

That's great to hear! If you want I can give a presentation about Triton-MLIR to anyone at Intel interested in the project. The "legacy" backend is definitely too coupled to Nvidia hardware; the new MLIR compilation pipeline should be much easier to modify -- especially if Intel GPUs have a warp size of 32 ... (do they?)

[chengjunlu]

@chengjunlu Maybe we could have a brief meeting together after we've finished MLIR rewriting? What do you think?

Sound's great.

BTW: in which branch the Triton-MLIR is developing? I want to have a quick ramp up.

[Jokeren]

https://github.com/openai/triton/tree/triton-mlir

Yeah, I had a talk with Xinmin Tian long time ago, not sure if he is still at Intel though.

[Jokeren]

I think there is some same concept in CUDA that to control logical warp size is configurable to reduce the register spill size. ("configurable warp size")

Can you please point me the related articles? I'm not aware of that in production code (not research papers).

[chengjunlu]

I think there is some same concept in CUDA that to control logical warp size is configurable to reduce the register spill size. ("configurable warp size")

Can you please point me the related articles? I'm not aware of that in production code (not research papers).

I am wrong about the CUDA has configurable warp size.
https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#hardware-multithreading

The configurable "warp size" is in Intel GPU because the GenX ISA is SIMD based and the compiler could chose the SIMD length for kernel.

[Jokeren]

Right, that matches what I thought. Thanks for the confirmation.

[chengjunlu]

@EikanWang Please share it on CPU aspect.

[Jokeren]

Since there's already the X86Vector Dialect https://mlir.llvm.org/docs/Dialects/X86Vector/ available, I suppose developing CPU ops could be fairly straightforward. I'm not sure if I miss something.

[ptillet]

The main challenge of writing a CPU backend for Triton will revolve around handling pointers -- AFAIK this is something that MLIR doesn't handle explicitly until LLVM codegen. We'll have to convert pointers (and tensors of pointers) to memrefs. But yeah, apart from that, a TritonToVector conversion pass seems relatively straightforward.

[chengjunlu]

Yeap.
It is still worth to investigate some Triton primitive to some specific systolic instruction which maybe not MLIR yet.

And also I think there is effort need to be spent in vendor/backend related optimization in the code gen.